| 1 Aug 2025 |
 emily | it looks like rva23u64 beats MIPS there | 12:09:20 |
| emily | so it's just a dumb comparison | 12:09:27 |
 K900 | Well yeah I don't mean this specific case | 12:09:37 |
| K900 | I just mean in general | 12:09:39 |
| emily | although the fragmentation of the RISC-V instruction sets in general is its own kind of dumb I suppose | 12:09:39 |
| emily | but also the thing teenage me would have done | 12:09:45 |
| K900 | There's like | 12:09:46 |
| K900 | A List | 12:09:47 |
| K900 | Of like Officially Mandated Fusions You Must Do To Fast | 12:10:01 |
| K900 | That compilers also know | 12:10:07 |
| emily | I think x86 also involves known uop fusions that compilers take into account | 12:10:08 |
| emily | it's arguably better to write it down than not | 12:10:15 |
| K900 | Not really | 12:10:17 |
| K900 | (for x86) | 12:10:23 |
| K900 | x86 mostly just has scheduling fuckery because it's very wide | 12:10:37 |
| K900 | But then modern aarch64 is also very wide | 12:10:46 |
| K900 | So it's likely actually fast RISC-V will also be very wide | 12:10:55 |
| K900 | So you'd have to consider both scheduling AND uop fusion and this is when you get the real funni | 12:11:12 |
| emily | my opinion as someone with no ISA design experience and no right to be making any judgement is that it feels like nobody has actually made anything better than AArch64 so far | 12:11:17 |
 dramforever | x86 and arm64 absolutely fuse | 12:11:24 |
| K900 | They do | 12:11:32 |
| K900 | But the compilers don't generally exploit it much | 12:11:42 |
| dramforever | meanwhile riscv is really geared toward the lower end | 12:11:44 |
| emily | but I get the impression that ARM gave up on Morello and all the CHERI energy is RISC-V these days | 12:12:24 |
| emily | so I'll probably end up having to care about RISC-V anyway :( | 12:12:32 |
| K900 | That's not what RISC-V people say | 12:12:36 |
| K900 | Though in practice it mostly is | 12:12:42 |
| emily | well marketing is one thing | 12:13:04 |
| dramforever | well sure, you don't want stuff like enter or loop in there even though a smol processor can microcode it | 12:13:46 |
| dramforever | also my headcanon is that rv{32,64}i is a prank by andrew waterman to try to get the most bare bones instruction set that upstream gcc and llvm supports | 12:14:14 |
