| 1 Aug 2025 |
 dramforever | In reply to @emilazy:matrix.org
"This is why LoongArch is better than RISC-V and also why the author of LoongArch does not like RISC-V and creates this new ISA." you saw that on reddit? that post was like, almost convincing in the opposite direction | 12:15:20 |
 K900 | Yes | 12:15:30 |
| dramforever | there has been a few really weird posts on r/riscv on this | 12:15:48 |
 emily | it has arithmetic right shift but not left shift. non-orthogonal. | 12:15:52 |
| emily | yes and I also saw the comments #debunking it | 12:16:01 |
| dramforever | addi but no subi | 12:16:18 |
| emily | but it does feel like the most baseline RISC-V architectures are like basically useless | 12:16:21 |
| emily | I guess you use them when you want to use five gates on your FPGA to implement 10 lines of logic | 12:16:37 |
| emily | and you want to do it in C for some reason | 12:16:48 |
| dramforever | rva20/rv64gc is painful | 12:16:59 |
| dramforever | rva22 is about right for now i think | 12:17:13 |
