| 1 Aug 2025 |
 emily | it's arguably better to write it down than not | 12:10:15 |
 K900 | Not really | 12:10:17 |
| K900 | (for x86) | 12:10:23 |
| K900 | x86 mostly just has scheduling fuckery because it's very wide | 12:10:37 |
| K900 | But then modern aarch64 is also very wide | 12:10:46 |
| K900 | So it's likely actually fast RISC-V will also be very wide | 12:10:55 |
| K900 | So you'd have to consider both scheduling AND uop fusion and this is when you get the real funni | 12:11:12 |
| emily | my opinion as someone with no ISA design experience and no right to be making any judgement is that it feels like nobody has actually made anything better than AArch64 so far | 12:11:17 |
 dramforever | x86 and arm64 absolutely fuse | 12:11:24 |
| K900 | They do | 12:11:32 |
| K900 | But the compilers don't generally exploit it much | 12:11:42 |
| dramforever | meanwhile riscv is really geared toward the lower end | 12:11:44 |
| emily | but I get the impression that ARM gave up on Morello and all the CHERI energy is RISC-V these days | 12:12:24 |
| emily | so I'll probably end up having to care about RISC-V anyway :( | 12:12:32 |
| K900 | That's not what RISC-V people say | 12:12:36 |
| K900 | Though in practice it mostly is | 12:12:42 |
| emily | well marketing is one thing | 12:13:04 |
| dramforever | well sure, you don't want stuff like enter or loop in there even though a smol processor can microcode it | 12:13:46 |
| dramforever | also my headcanon is that rv{32,64}i is a prank by andrew waterman to try to get the most bare bones instruction set that upstream gcc and llvm supports | 12:14:14 |
| emily | how easy is it to get LoongArch hardware anyway? seems like a lot of Chinese hobbyists have their hands on it but I've never heard of anyone elsewhere running it | 12:14:47 |
| emily | https://msyksphinz-self.github.io/riscv-isadoc/html/rvi.html is this really every single instruction in RV32I | 12:15:15 |
| dramforever | In reply to @emilazy:matrix.org
"This is why LoongArch is better than RISC-V and also why the author of LoongArch does not like RISC-V and creates this new ISA." you saw that on reddit? that post was like, almost convincing in the opposite direction | 12:15:20 |
| K900 | Yes | 12:15:30 |
| dramforever | there has been a few really weird posts on r/riscv on this | 12:15:48 |
| emily | it has arithmetic right shift but not left shift. non-orthogonal. | 12:15:52 |
| emily | yes and I also saw the comments #debunking it | 12:16:01 |
| dramforever | addi but no subi | 12:16:18 |
| emily | but it does feel like the most baseline RISC-V architectures are like basically useless | 12:16:21 |
| emily | I guess you use them when you want to use five gates on your FPGA to implement 10 lines of logic | 12:16:37 |
| emily | and you want to do it in C for some reason | 12:16:48 |
