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1 Aug 2025
@emilazy:matrix.orgemilybut it does feel like the most baseline RISC-V architectures are like basically useless12:16:21
@emilazy:matrix.orgemilyI guess you use them when you want to use five gates on your FPGA to implement 10 lines of logic12:16:37
@emilazy:matrix.orgemilyand you want to do it in C for some reason12:16:48
@dramforever:matrix.orgdramforeverrva20/rv64gc is painful12:16:59
@dramforever:matrix.orgdramforeverrva22 is about right for now i think12:17:13
@dramforever:matrix.orgdramforeverrva23 we'll see in 203012:17:21

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