| 25 Nov 2023 |
| @yvtjp:matrix.org joined the room. | 02:39:51 |
| 26 Nov 2023 |
| pinpox joined the room. | 13:00:30 |
| 27 Nov 2023 |
| scm joined the room. | 21:30:45 |
| 4 Dec 2023 |
| ctem joined the room. | 15:36:47 |
| 5 Dec 2023 |
| Federico Damián Schonborn changed their profile picture. | 00:38:50 |
fgaz | DRM under review 👀 https://rvspace.org/en/project/JH7110_Upstream_Plan | 10:17:17 |
Pratham Patel (you can mention me) | On that note, we are waiting for a new patchset for PCIe, right? | 10:22:18 |
| 6 Dec 2023 |
misuzu | Updated efi images: https://github.com/misuzu/nixos-vf2/releases/tag/0.6 | 10:39:38 |
misuzu | https://www.reddit.com/r/RISCV/comments/18ban5m/any_announcements_on_the_starfive_jh8100/ | 13:31:10 |
| 7 Dec 2023 |
tau | In reply to @fgaz:matrix.org DRM under review 👀 https://rvspace.org/en/project/JH7110_Upstream_Plan what about the GPU ? i don't see it on this list | 00:42:58 |
tau | i guess it's only blobs | 00:47:17 |
tau | https://github.com/starfive-tech/soft_3rdpart/tree/JH7110_VisionFive2_devel/IMG_GPU/out | 00:47:19 |
| tau changed their display name from Ms. Demeanor to Mr. Worm. | 06:17:40 |
| tau changed their display name from Mr. Worm to Dr. Worm. | 06:19:52 |
| tau changed their profile picture. | 06:21:35 |
| 8 Dec 2023 |
| tau changed their profile picture. | 01:53:29 |
fgaz | gcc is broken in staging
gcc-13.2.0/libgcc/config/riscv/value-unwind.h:32: Error: unrecognized opcode `0xc2202573'
I don't understand why it tries to do that when we set the architecture to riscv64gc | 14:14:11 |
| pouspous joined the room. | 20:15:36 |
| 9 Dec 2023 |
| Digital Pirate joined the room. | 08:14:35 |
Alex | In reply to @fgaz:matrix.org
gcc is broken in staging
gcc-13.2.0/libgcc/config/riscv/value-unwind.h:32: Error: unrecognized opcode `0xc2202573'
I don't understand why it tries to do that when we set the architecture to riscv64gc NB: According to the RISC-V ISA manual (V20211203), that is a CSRRS instruction on CSR 0xc22, which is a standard read-only unprivileged CSR that hasn't yet been allocated. Whatever is generating that instruction probably should not.
If you don't need CSRs, disabling Zicsr may help. | 13:23:25 |