| 16 Jun 2023 |
 raitobezarius | In reply to @misuzu:matrix.org
*for nvme boot ah yes yes correct | 11:34:13 |
 misuzu | In reply to @alex:tunstall.xyz
Newer versions of the vendor's bootloader might support NVMe boot.
https://github.com/starfive-tech/VisionFive2/blob/8b7a21b808e02d996dc166d70f2675a059c2e1ed/conf/vf2_nvme_uEnv.txt Their distroboot config doesn't support nvme | 11:36:00 |
| 17 Jun 2023 |
 @lotte:chir.rs | I ended up moving the install to iscsi | 15:44:44 |
| @lotte:chir.rs | but it works now 🦀 | 15:44:50 |
| @lotte:chir.rs | semi related thing i just noticed, the vf2 apparently supports the Zbb extension | 15:45:35 |
| @lotte:chir.rs | and then i noticed that gcc was outputting suboptimal assembly for a test case but it’s fixed already | 15:46:08 |
| @lotte:chir.rs | https://godbolt.org/z/eEvcbqGYn | 15:46:08 |
 Alex | In reply to @lotte:chir.rs
semi related thing i just noticed, the vf2 apparently supports the Zbb extension Yes, it also has Zba despite neither being mentioned in the vendor's documentation. | 15:52:38 |
| @lotte:chir.rs | iirc the core ip they licensed does advertise support for the “B extension” | 15:53:18 |
| @lotte:chir.rs | and so does the IPL/firmware | 15:53:28 |
| Alex | For the SiFive U74, Zba and Zbb appear to be optional, so I'm not sure every CPU variant have them. | 15:54:39 |
| @lotte:chir.rs | yeah | 15:57:38 |
| @lotte:chir.rs | okay i just verified that, Zbc and Zbc are not supported | 16:17:17 |
| @lotte:chir.rs | * okay i just verified that; Zbc and Zbc are not supported | 16:17:24 |
| @lotte:chir.rs | * okay i just verified that; Zbc and Zbs are not supported | 16:17:31 |
| Alex | In reply to @lotte:chir.rs
iirc the core ip they licensed does advertise support for the “B extension” By the way, SiFive call it "RV64GBC", but it's actually "RV64GC_Zba_Zbb"; only the latter works with GCC's -march flag (GCC >=12). | 17:09:09 |
| @lotte:chir.rs | yeah it’s why i put it in quotes | 17:09:40 |
| @lotte:chir.rs | the B extension is nowhere near ratified and it’s a lot more complicated than a bit of shifted adding, rotation, and additional ALU outputs | 17:10:32 |
| @lotte:chir.rs | * the B extension is nowhere near ratified and it’s a lot more complicated than a bit of shifted adding, rotation, and ALU ops that just require a bit of extra control logic | 17:11:12 |
| @lotte:chir.rs | (andn, orn, and xnor is what sub is to add basically) | 17:11:30 |
| @lotte:chir.rs | * the B extension is nowhere near ratified and it’s a lot more complicated than a bit of shift-adding, rotation, and ALU ops that just require a bit of extra control logic | 17:12:02 |
| 18 Jun 2023 |
|  quasineutral joined the room. | 09:50:10 |
| @lotte:chir.rs | I wonder what the extension instructions are on the jh7110 | 15:10:10 |
| @lotte:chir.rs | * I wonder what the custom instructions are on the jh7110 | 15:10:18 |
| 25 Jun 2023 |
 Alyssa Ross | ugh, loongarch64 linux includes the kernel version number in the name of the image it installs, so we can't use our normal kernelTarget mechanism | 13:49:13 |
| Alyssa Ross | (although tbh, I've been wanting to change how kernelTarget works for a while. It doesn't really make sense for it to be a platform property. It should be an option + passthru on the kernel derivation.) | 13:49:39 |
| 26 Jun 2023 |
| raitobezarius | https://twitter.com/Houge_Langley/status/1673110240647331840 | 09:38:52 |
| Alex | In reply to @raitobezarius:matrix.org
https://twitter.com/Houge_Langley/status/1673110240647331840 If they're using upstream Nixpkgs, it's probably going to fail on LLVM 11; adding an overlay for llvmPackages = self.llvmPackages_15 should fix it. | 09:42:38 |
| raitobezarius | Redacted or Malformed Event | 09:42:48 |
| raitobezarius | We will see what OP says :) | 09:43:06 |
