| 4 Apr 2024 |
|  rtunreal joined the room. | 15:23:24 |
|  jopejoe1 joined the room. | 16:22:35 |
 tau | Redacted or Malformed Event | 18:06:30 |
| tau | sorry not what i meant to post | 18:06:52 |
| tau | i finally got a build failure that was just tests | 18:07:10 |
| tau | this is going to make things difficult,,, | 18:07:19 |
| tau | catch2-3.5.2-riscv64-linux | 18:07:20 |
 sorear | the C910 has two classes of issues:
- non-standard features for things that eventually became standard, i.e. RVV 0.7.1, MAEE instead of Svpbmt (needed for PCIe because Intel didn't distinguish BARs by memory type, irrelevant otherwise), T-Head performance counters, etc. None of this affects software that doesn't opt in to using the pre-standard feature, and none of it is morally different from any other non-standard extension, which are likely to be ubiquitous
- ordinary bugs - unreasonably slow contended memory access without fences, wrong decoding of noncanonical fences, wrong FP underflow flag - there is no reason to believe that future, more complicated cores will have fewer total bugs, even if they fix the current bugs, and also no evidence that the C910's crop of bugs can cause successful builds with miscompilations
| 18:24:49 |
| sorear | I can't imagine a consistent standard which would (a) rule out the use of the C910 for non-test builds (b) not rule out every other piece of hardware which exists in the past and future for the same reason | 18:25:50 |
 Pratham Patel (you can mention me) | The SiFive J74 cores in the Unmatched and the VF2 are pretty spec compliant AFAIK | 18:30:07 |
| sorear | are those the ones that can't correctly handle a sfence instruction with a nonzero virtual address and get the trap PC wrong when you jump to a negative noncanonical VA? | 18:32:03 |
| sorear | sifive is better at communicating errata in english, I'll give them that much | 18:32:36 |
| sorear | I specifically want to avoid a policy which requires no public errata, because that will just push us towards vendors that treat all errata as trade secrets | 18:33:04 |
| Pratham Patel (you can mention me) | me not know that, I’ll look into that tomorrow | 18:34:07 |
 Alex | In reply to @hive:the-apothecary.club
catch2-3.5.2-riscv64-linux I've already encountered this build failure. Here's a fix (probably suboptimal, but it works). | 19:18:21 |
| tau | thanks :fold | 19:19:44 |
| tau | * thanks 🙏 | 19:19:49 |
| Alex | (The fix is based on skeuchel's PR. You could probably use that PR directly if you use a custom Nixpkgs repository; I don't.) | 19:20:37 |
| tau | i don't either | 19:20:50 |
|  silvanshade joined the room. | 19:42:09 |
| 5 Apr 2024 |
|  liberodark joined the room. | 07:46:35 |
| liberodark | Hi | 11:27:42 |
| liberodark | If you need to work on RISC-V servers, don't hesitate to ask me, I will provide some for free. | 11:28:51 |
| liberodark | being also a small user of nixos it is important to me that everyone can work in good conditions. To improve this architecture. | 11:30:25 |
| Pratham Patel (you can mention me) | Nice work, thank you
- a NixOS user | 11:31:00 |
| Alex | In reply to @liberodark:matrix.org
If you need to work on RISC-V servers, don't hesitate to ask me, I will provide some for free. Are you able to share the specs of those servers? Esp. CPU model | 11:31:17 |
| liberodark | I don't want to advertise here so I won't put the link to my RISC-V project here, I don't want to spam but don't hesitate to ping me. | 11:31:28 |
| liberodark | In reply to @alex:tunstall.xyz
Are you able to share the specs of those servers? Esp. CPU model Yes | 11:31:34 |
| liberodark | Im go to share C920 C910 & JH7110 | 11:31:56 |
| liberodark | * Im go to share SoC : C920 C910 & JH7110 | 11:34:06 |
