| 8 Apr 2024 |
 Steven Keuchel | hope it works now | 10:26:34 |
| 9 Apr 2024 |
 Pratham Patel (you can mention me) | sorear: https://www.theregister.com/2024/04/09/sifive_riscv_hifive/ | 07:02:44 |
|  SomeoneSerge (migrating synapse) changed their display name from SomeoneSerge (migrating synapse) to SomeoneSerge (void). | 13:23:23 |
 tau | i'm surprised you haven't dealt with zeromq, because nix why-depends says systemd depends on it :
» nix why-depends --derivation nixpkgs#systemd nixpkgs#zeromq
/nix/store/mmxfq68bslpjqki0f7svg31cjv2pnr36-systemd-255.2.drv
└───/nix/store/js89ydnz71fv1kqgn69mm7yqfsw61lpi-iptables-1.8.10.drv
└───/nix/store/5b85c19psp7km2mvnlwzs0gml93v289x-libpcap-1.10.4.drv
└───/nix/store/rpgg2wwh745g9y928wb6a2w1gn23g9y1-libnl-3.8.0.drv
└───/nix/store/hks3p38b5vdjkncdkkrcwjjqlhg1cbs7-graphviz-10.0.1.drv
└───/nix/store/s5pcbnaqw75bxbyk3hyb2kmjr0b1viab-fontconfig-2.15.0.drv
└───/nix/store/q124gz30q037qq5n6vnym3n2gkf6r4n9-dejavu-fonts-minimal-2.37.drv
└───/nix/store/rngadqxkfwizz368b9zg3az9ifdgfgsn-dejavu-fonts-full-2.37.drv
└───/nix/store/rhw4k7zqgrvw36rz6cq5m6p12afpwc7l-fontforge-20230101.drv
└───/nix/store/ir6k22cspdsw25l4jskfrlmymhyr30g5-zeromq-4.3.5.drv
| 21:09:15 |
|  Shalok Shalom left the room. | 21:09:27 |
 Alex | Why? Is there something wrong with zeromq on RISC-V?
I don't seem to have a fix for it and my full system rebuild is complete, so it should work fine. | 21:59:50 |
| tau | Download zeromq-log.txt | 22:11:14 |
| tau | won't build for me on qemu | 22:12:42 |
|  KREYREN ⚡️🦀 (TH1520 in Licheepi 4A) changed their profile picture. | 23:12:30 |
| 10 Apr 2024 |
| Pratham Patel (you can mention me) | misuzu: is there any reason why you are using the vendor kernel? AFAIK, everything but PCIe (for a headless build box) has been merged upstream. Or did I just answer myself with "PCIe isn't yet in upstream?" | 02:10:37 |
 sorear | In reply to @thefossguy:matrix.org
sorear: https://www.theregister.com/2024/04/09/sifive_riscv_hifive/ will be interesting to see how this plays out with their documentation commitment, the GPU, and where they are going to position themselves (price, features, volume) relative to other SBC manufacturers. doesn't seem very specific to (a) me (b) nixos though | 04:07:37 |
| Pratham Patel (you can mention me) | pinged you by mistake, the person I wanted to mention isn't in this room | 04:08:40 |
| Pratham Patel (you can mention me) | but relevant to nixos since it's a good machine to have until Oasis launches with 128GB of DRAM | 04:09:05 |
| Pratham Patel (you can mention me) | Instead of boards with recent T-Head cores | 04:10:02 |
| sorear | if you believe their claims about shipping dates, which I firmly don't | 04:10:06 |
| Pratham Patel (you can mention me) | I don't believe it until it's in my hands | 04:10:30 |
| Pratham Patel (you can mention me) | but it's a good estimate :) | 04:10:36 |
| sorear | not that I mind shaking out reproducibility issues and finding bugs in (both!) cores by building things using both p550 and c920v2 | 04:10:55 |
| Pratham Patel (you can mention me) | :) | 04:11:10 |
| sorear | having andrew on the team is likely to result in fewer cases of "blatantly misunderstood the spec" but there's still a ton that can go wrong | 04:11:43 |
| sorear | actually that probably doesn't help because they're probably big enough that the silicon teams don't talk to the ISA experts | 04:12:28 |
| Pratham Patel (you can mention me) | we'll see the real deal when upstreaming starts and they need to disclose the erratas | 04:12:58 |
| Alex | In reply to @thefossguy:matrix.org
misuzu: is there any reason why you are using the vendor kernel? AFAIK, everything but PCIe (for a headless build box) has been merged upstream. Or did I just answer myself with "PCIe isn't yet in upstream?" Unless it's been integrated in the past week, mainline also appears to be missing the PLL0 patch needed for running the CPU at 1.5 GHz instead of 1 GHz. | 08:23:01 |
 @cnx:loang.net | In reply to @thefossguy:matrix.org
misuzu: is there any reason why you are using the vendor kernel? AFAIK, everything but PCIe (for a headless build box) has been merged upstream. Or did I just answer myself with "PCIe isn't yet in upstream?" is pcie required for nvme? | 08:24:23 |
| Pratham Patel (you can mention me) | In reply to @alex:tunstall.xyz
Unless it's been integrated in the past week, mainline also appears to be missing the PLL0 patch needed for running the CPU at 1.5 GHz instead of 1 GHz. A v4 was sent today morning | 08:24:53 |
| Alex | In reply to @cnx:loang.net
is pcie required for nvme? I'd be very surprised if it isn't. | 08:25:00 |
| Pratham Patel (you can mention me) | In reply to @cnx:loang.net
is pcie required for nvme? NVMe is over PCIe, so yes | 08:25:31 |
| Pratham Patel (you can mention me) | In reply to @thefossguy:matrix.org
A v4 was sent today morning A v5 will happen but that should be the final one.
https://lore.kernel.org/linux-riscv/20240410033148.213991-1-xingyu.wu@starfivetech.com/T/#mc21269f266c6a7207416d57c98d5f4d64d46cf89 | 08:39:07 |
|  ohyeah joined the room. | 18:31:00 |
 misuzu | In reply to @thefossguy:matrix.org
misuzu: is there any reason why you are using the vendor kernel? AFAIK, everything but PCIe (for a headless build box) has been merged upstream. Or did I just answer myself with "PCIe isn't yet in upstream?" yep | 19:52:45 |
