| 19 Feb 2024 |
 Pratham Patel (you can mention me) | the last tenstorrent event almost a year ago in BLR was exactly that :) | 14:35:15 |
 sorear | it's hard to exhaustively test anything of that size, especially when the specs themselves are nondeterministic (memory ordering, counters) or just plain ambiguous | 14:37:22 |
 Alex | In reply to @sorear:matrix.org
it's hard to exhaustively test anything of that size, especially when the specs themselves are nondeterministic (memory ordering, counters) or just plain ambiguous Yes, that's very fair. I'd expect some amount of testing to be possible by exploiting a deep understanding of the processor design, but that's by no means simple. | 14:39:43 |
| sorear | the interesting bugs all happen because somebody miscommunicated or misunderstood the requirements | 14:40:34 |
| Pratham Patel (you can mention me) | one thing I--as a software guy and a negative XP in hardware--understand is, at that point, you're not just verifying the RISC-V ISA but also the microarchitecture :) | 14:40:47 |
| * Pratham Patel (you can mention me) is afk for dinner | 14:40:54 |
