| 7 Jul 2025 |
|  Jack Leightcap left the room. | 18:10:24 |
| 8 Jul 2025 |
 zimward | i was thinking about what it would take to setup a official builder to populate the cache with riscv packages together with rtunreal. so far we thought about either one or two milkv pioneer boards or a cluster of Systems on a module like the one from milkv or simmilar in a 1 or 2 U chassis. whats the general stance about setting up something like this? also im not sure what the impact of GhostWrite is on compiling (ie how bad it disableing vector is for the performance), any input is appreciated. | 18:48:18 |
| zimward | Redacted or Malformed Event | 18:48:18 |
 Tristan Ross | I like it, I think it would be great for someone to bring this up with the NixOS hardware team. I've been wanting this to happen. If there's more motivation outside the team, I can support it. | 19:15:32 |
 rtunreal | We would try to get in touch and plan/set up the infrastructure for this to happen. We also would want to have the opinions of people like Nick Cao and misuzu (who currently host the biggest Risc-V cache?) so we could have their opinion and coordinate a smooth roll-over, as we don't want to do it over their head. | 19:19:04 |
| zimward | getting in touch with the infra team would probably also good to get some knowledge about the current requirements of the builders (as in storage, peak memory usage of jobs, etc) | 19:22:18 |
| Tristan Ross | I just know that at least on the HW team side of things, we've floated ideas for Hydra and caches. RISC-V is a big thing I want to see supported because it's newer and isn't supported well right now by nixpkgs. | 19:27:07 |
| Tristan Ross | With my stdenv hat on though, I want to see it become a tier 2 target rather than tier 3. | 19:27:34 |
| zimward | considering the inertia riscv has and will probably sustain (see china and europes riscv effords) we should definetly aim to get it close to arm's support in the long term | 19:29:50 |
| Tristan Ross | Yeah, as a user who daily drives arm, I do want it to become tier 1. | 19:30:54 |
| Tristan Ross | Fun fact, the stdenv team added a new target triple question to the survey. We'll use this to better effectively handle supporting targets. | 19:34:05 |
|  ra33it0 joined the room. | 19:57:18 |
| 9 Jul 2025 |
 dramforever | re: riscv i think we should probably wait for more reliable hardware | 00:58:29 |
| dramforever | which should be soon-ish (as in within a year) | 00:58:48 |
| dramforever | within this year probably if we get eswin eic770* | 00:59:32 |
| dramforever | In reply to @zimward:zimward.moe
i was thinking about what it would take to setup a official builder to populate the cache with riscv packages together with rtunreal. so far we thought about either one or two milkv pioneer boards or a cluster of Systems on a module like the one from milkv or simmilar in a 1 or 2 U chassis. whats the general stance about setting up something like this? also im not sure what the impact of GhostWrite is on compiling (ie how bad it disableing vector is for the performance), any input is appreciated. the impact on generic software is zero | 01:00:04 |
| dramforever | gcc and llvm both support -march=+xtheadvector but ~nobody is using that | 01:00:47 |
| dramforever | i do wonder where SG2044 is at | 01:03:30 |
| dramforever | it should be just SG2042 but better | 01:03:41 |
| Tristan Ross | In reply to @dramforever:matrix.org
re: riscv i think we should probably wait for more reliable hardware I definitely don't disagree on this but like, I do want to see something heh. | 01:09:20 |
| Tristan Ross | In reply to @dramforever:matrix.org
it should be just SG2042 but better How does it compare to the P550? | 01:09:46 |
| Tristan Ross | Oh, it has P550 cores | 01:18:06 |
| dramforever | SG2044 isn't P550 | 01:32:50 |
| dramforever | Ot' | 01:32:52 |
| dramforever | * It's supposedly C920v2 | 01:32:59 |
| dramforever | but these names don't mean anything anymore | 01:33:06 |
| dramforever | basically SG2042 but better | 01:33:11 |
| dramforever | with ratified V | 01:33:15 |
| Tristan Ross | I was looking at this https://www.cnx-software.com/2024/06/19/eswin-eic7700x-quad-core-risc-v-soc-embeds-19-95-tops-npu-for-edge-ai-vision-applications/ | 01:53:09 |
| dramforever | oh, yes, eic7700x is p550 | 03:13:08 |
