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NixOS RISC-V

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NixOS on RISC-V https://wiki.nixos.org/wiki/RISC-V https://pad.lassul.us/NixOS-riscv64-linux https://github.com/orgs/NixOS/teams/risc-v63 Servers

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29 Jul 2025
@rosscomputerguy:matrix.orgTristan Ross I just got tt-smi working 17:32:07
@rosscomputerguy:matrix.orgTristan Ross https://github.com/RossComputerGuy/tenstorrent.nix/commit/cb564332bb90714cb62a8ffeebd370f72f02c89f 17:32:47
@rosscomputerguy:matrix.orgTristan Ross https://github.com/tenstorrent/luwen/pull/98 luwen will have this soon 17:35:28
3 Aug 2025
@dramforever:matrix.orgdramforever just throwing this out there, has anyone tried ubootVisionFive2 without the opensbi override? 11:56:31
@dramforever:matrix.orgdramforeveri have a feeling that the u-boot docs at https://docs.u-boot.org/en/latest/board/starfive/visionfive2.html#building have been written while assuming a non-PIE-capable toolchain11:59:38
@dramforever:matrix.orgdramforeversupport for non-PIE boot was outright removed in opensbi since11:59:53
@dramforever:matrix.orgdramforever* support for non-PIE build was outright removed in opensbi since12:00:00
@dramforever:matrix.orgdramforever the current FW_TEXT_START is effectively a "degree of freedom" in the build where it's basically added to symbols at build and subtracted during relocation, as a convenience for debugging 12:01:23
@dramforever:matrix.orgdramforeverwell by "the opensbi override" i mean https://github.com/NixOS/nixpkgs/blob/53c766aff17166404ccdf31c687ac63eab9f2457/pkgs/misc/uboot/default.nix#L849-L85712:05:12
6 Aug 2025
@dramforever:matrix.orgdramforeverpr for testing if you want to but i don't see what could go wrong https://github.com/NixOS/nixpkgs/pull/43141310:59:00
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@dramforever:matrix.orgdramforeverScreenshot_20250822_143818.png
Download Screenshot_20250822_143818.png
06:43:34
@dramforever:matrix.orgdramforever looking forward to the -j64ability on sg2044 https://arxiv.org/abs/2508.13840 06:43:43
@rosscomputerguy:matrix.orgTristan Ross
In reply to @dramforever:matrix.org
Screenshot_20250822_143818.png
Actual 64 cores of RISC-V? Are we starting to see Ampere levels of cores for RISC-V lol
07:12:41
@zimward:zimward.moezimwardthe SG2042 also had 64 cores, but the ghostwrite bug makes that chip really unviable07:18:57
@zimward:zimward.moezimward* on the SG2042 the ghostwrite bug makes that chip really unviable07:19:33
@dramforever:matrix.orgdramforeverampere number of cores07:33:42

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