| 8 Jul 2025 |
 Tristan Ross | With my stdenv hat on though, I want to see it become a tier 2 target rather than tier 3. | 19:27:34 |
 zimward | considering the inertia riscv has and will probably sustain (see china and europes riscv effords) we should definetly aim to get it close to arm's support in the long term | 19:29:50 |
| Tristan Ross | Yeah, as a user who daily drives arm, I do want it to become tier 1. | 19:30:54 |
| Tristan Ross | Fun fact, the stdenv team added a new target triple question to the survey. We'll use this to better effectively handle supporting targets. | 19:34:05 |
|  ra33it0 joined the room. | 19:57:18 |
| 9 Jul 2025 |
 dramforever | re: riscv i think we should probably wait for more reliable hardware | 00:58:29 |
| dramforever | which should be soon-ish (as in within a year) | 00:58:48 |
| dramforever | within this year probably if we get eswin eic770* | 00:59:32 |
| dramforever | In reply to @zimward:zimward.moe
i was thinking about what it would take to setup a official builder to populate the cache with riscv packages together with rtunreal. so far we thought about either one or two milkv pioneer boards or a cluster of Systems on a module like the one from milkv or simmilar in a 1 or 2 U chassis. whats the general stance about setting up something like this? also im not sure what the impact of GhostWrite is on compiling (ie how bad it disableing vector is for the performance), any input is appreciated. the impact on generic software is zero | 01:00:04 |
| dramforever | gcc and llvm both support -march=+xtheadvector but ~nobody is using that | 01:00:47 |
| dramforever | i do wonder where SG2044 is at | 01:03:30 |
| dramforever | it should be just SG2042 but better | 01:03:41 |
| Tristan Ross | In reply to @dramforever:matrix.org
re: riscv i think we should probably wait for more reliable hardware I definitely don't disagree on this but like, I do want to see something heh. | 01:09:20 |
| Tristan Ross | In reply to @dramforever:matrix.org
it should be just SG2042 but better How does it compare to the P550? | 01:09:46 |
| Tristan Ross | Oh, it has P550 cores | 01:18:06 |
| dramforever | SG2044 isn't P550 | 01:32:50 |
| dramforever | Ot' | 01:32:52 |
| dramforever | * It's supposedly C920v2 | 01:32:59 |
| dramforever | but these names don't mean anything anymore | 01:33:06 |
| dramforever | basically SG2042 but better | 01:33:11 |
| dramforever | with ratified V | 01:33:15 |
| Tristan Ross | I was looking at this https://www.cnx-software.com/2024/06/19/eswin-eic7700x-quad-core-risc-v-soc-embeds-19-95-tops-npu-for-edge-ai-vision-applications/ | 01:53:09 |
| dramforever | oh, yes, eic7700x is p550 | 03:13:08 |
 fgaz | we do have eic7700x boards though, i have one on my desk | 09:02:57 |
| dramforever | to be honest, i'm not sure why i said "this year". i know milkv megrez very much exists now | 09:18:12 |
| dramforever | * to be honest, i'm not sure why i said "this year". i knew milkv megrez very much exists now | 09:18:17 |
| dramforever | maybe i was thinking about the software situation | 09:18:27 |
| fgaz | or eic7702 | 09:59:40 |
| fgaz | that one is still not out, is it? | 10:00:07 |
| zimward | In reply to @dramforever:matrix.org
re: riscv i think we should probably wait for more reliable hardware what do you mean with more reliable hardware? (i would assume that most current SBCs will run fine without crashing) the builders don't need good single core performance as long as we can get enough cores with the memory to support them in a small enough form factor to cram them in a 1 or 2U chassis. | 10:04:33 |
