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NixOS RISC-V

228 Members
NixOS on RISC-V https://wiki.nixos.org/wiki/RISC-V https://pad.lassul.us/NixOS-riscv64-linux https://github.com/orgs/NixOS/teams/risc-v70 Servers

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27 Jun 2025
@0x4a6f:matrix.org[0x4A6F]Who wants an invitation to the team? 👋16:08:46
@dramforever:matrix.orgdramforeveri have requested16:21:15
@lotte:chir.rs@lotte:chir.rsi can’t access the link16:22:19
@dramforever:matrix.orgdramforeveri wonder if you need to be already a member of nixos org or something16:27:25
@lotte:chir.rs@lotte:chir.rsvery likely16:27:37
@dramforever:matrix.orgdramforeveryou can wait for an invite coming any second now16:27:46
@0x4a6f:matrix.org[0x4A6F]What's your GitHub username?16:29:27
@lotte:chir.rs@lotte:chir.rsDarkKirb16:31:03
@0x4a6f:matrix.org[0x4A6F]Can't invite you: Not a member of this organisation16:32:07
@lotte:chir.rs@lotte:chir.rsmakes sense16:32:23
29 Jun 2025
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@jonhermansen:matrix.org@jonhermansen:matrix.org I'd like one, if possible! I am interested in helping test and fix issues on RISC-V. I am looking into setting up qemu-user locally myself, since I don't have physical hardware at the moment. I should already be a part of NixOS org, I got added yesterday.

https://github.com/jonhermansen/
19:03:09
6 Jul 2025
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7 Jul 2025
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8 Jul 2025
@zimward:zimward.moezimward i was thinking about what it would take to setup a official builder to populate the cache with riscv packages together with rtunreal. so far we thought about either one or two milkv pioneer boards or a cluster of Systems on a module like the one from milkv or simmilar in a 1 or 2 U chassis. whats the general stance about setting up something like this? also im not sure what the impact of GhostWrite is on compiling (ie how bad it disableing vector is for the performance), any input is appreciated. 18:48:18
@zimward:zimward.moezimwardRedacted or Malformed Event18:48:18
@rosscomputerguy:matrix.orgTristan RossI like it, I think it would be great for someone to bring this up with the NixOS hardware team. I've been wanting this to happen. If there's more motivation outside the team, I can support it.19:15:32
@rtunreal:c-base.orgrtunrealWe would try to get in touch and plan/set up the infrastructure for this to happen. We also would want to have the opinions of people like Nick Cao and misuzu (who currently host the biggest Risc-V cache?) so we could have their opinion and coordinate a smooth roll-over, as we don't want to do it over their head.19:19:04
@zimward:zimward.moezimwardgetting in touch with the infra team would probably also good to get some knowledge about the current requirements of the builders (as in storage, peak memory usage of jobs, etc)19:22:18
@rosscomputerguy:matrix.orgTristan RossI just know that at least on the HW team side of things, we've floated ideas for Hydra and caches. RISC-V is a big thing I want to see supported because it's newer and isn't supported well right now by nixpkgs.19:27:07

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