Sender | Message | Time |
---|---|---|
8 Apr 2024 | ||
Alex | This can also be found in the vendor's official documentation: https://doc-en.rvspace.org/VisionFive2/Boot_UG/JH7110_SDK/boot_address_allocation.html Now whether or not those offsets are important is still unknown. | 09:34:00 |
Alex | The official documentation is also missing one critical detail: the partition type IDs. | 09:35:38 |
@cnx:loang.net | thanks! | 09:37:28 |
Pratham Patel (you can mention me) | In reply to @alex:tunstall.xyzdo you mean these? https://docs.u-boot.org/en/latest/board/starfive/visionfive2.html#flashing | 09:38:33 |
Alex | Yes, those typecode UUIDs for partition 1 and 2 are necessary. | 09:39:15 |
Pratham Patel (you can mention me) | i usually never go back to vendor docs once upstreaming starts :) | 09:39:54 |
Alex | I'm quite thankful that they at least have some documentation. Not everyone wants to read Linux kernel code and dts files to figure out where the UART device and SRAM are. | 09:42:10 |
Pratham Patel (you can mention me) | They ought to have at least this much provided | 09:42:36 |
Alex | They have a (nearly) complete description of the entire physical memory map. If only I could remember which document it's in... | 09:43:17 |
Pratham Patel (you can mention me) | Yeah, JH7110 is surprisingly "open". | 09:43:44 |
Alex | Here it is: https://doc-en.rvspace.org/JH7110/TRM/JH7110_TRM/system_memory_map.html | 09:44:09 |
Steven Keuchel | In reply to @alex:tunstall.xyzI was usually also compiling something else. I think the registerised ones are more accurate. | 09:58:10 |
Steven Keuchel | In reply to @alex:tunstall.xyzyes exactly, you need https://gitlab.haskell.org/ghc/ghc/-/merge_requests/10714 and https://gitlab.haskell.org/ghc/ghc/-/merge_requests/12286 | 09:59:04 |
Steven Keuchel | I wanted to create a nixpkgs PR once the the second one is merged upstream. | 09:59:53 |
Steven Keuchel | be careful though, one has to be added to the hadrian derivation and the other to the ghc derivation | 10:00:31 |
Alex | Well damn, I'm already 3h into a build with both on the GHC derivation ๐ I assume your Hadrian PR goes into the Hadrian derivation? | 10:01:49 |
Steven Keuchel | here is the part of my overlay that does this
| 10:02:15 |
Alex | Your hash for 10714 doesn't match mine... Is that commit still fetchable? | 10:05:17 |
Steven Keuchel | grr, I hate fetchpatch | 10:05:58 |
Steven Keuchel | let me gc and try to fix it | 10:06:08 |
Alex | I'm fetching the entire MR, so that might be why (but the other one matches) | 10:08:12 |
Alex | Yep, build fails with your hash. Correct one is sha256-uonXubXjMywSbUe/p2HLIWXDpwLWHlpZDMBvDnr/Utc= | 10:14:13 |
Alex | Oh wait, I was missing stripLen . Nevermind. | 10:17:10 |
Steven Keuchel | oh ok :D I had it as a file before and switched to fetchpatch before posting | 10:26:13 |
Steven Keuchel | hope it works now | 10:26:34 |
9 Apr 2024 | ||
Pratham Patel (you can mention me) | sorear: https://www.theregister.com/2024/04/09/sifive_riscv_hifive/ | 07:02:44 |
SomeoneSerge (utc+3) changed their display name from SomeoneSerge (migrating synapse) to SomeoneSerge (void). | 13:23:23 | |
Li-ion | i'm surprised you haven't dealt with zeromq, because nix why-depends says systemd depends on it : | 21:09:15 |
@shalokshalom:kde.org left the room. | 21:09:27 | |
Alex | Why? Is there something wrong with zeromq on RISC-V? I don't seem to have a fix for it and my full system rebuild is complete, so it should work fine. | 21:59:50 |